(a). Field of the Invention
The present invention relates to a phase switch circuit. Especially, the present invention relates to a phase switch circuit that can switch bi-directionally and avoid glitch/spike.
(b). Description of the Prior Arts
In a data recovery system, the high frequency of the received signal that declining and impacted by the noise of media will be recovered by a equalizer, however, a correct sampling of data stream still depends on a precise clock. The rising/falling edge of the clock needs to align precisely to the middle of data stream to obtain correct sampling. In prior art, a data recovery system employs a continuous time Phase-Locked Loop (PLL) to complete the job of clock recovery, and with which align with the data stream received and the sampling clock. The disadvantages of clock recovery that employing the continuous time PLL are as follows: (1) longer lock time (2) influence of phase noise (3) only providing one receive channel.
In current trend of technology, the multiple phase system will be adapted to handle the clock recovery that described above. With the switch of phase signal, the proper phase signal being selected in the multiple phase system will make the rising/falling edge of the recovered sampling clock align preciously to the middle of the data stream, which will theoretically make bit error rate to the minimum level. The rapid lock-in is the advantage of using the switch of multiple phases to handle the clock recovery, that is, the lock-in will be completed only in few clock cycle, and since most calculation is in digital format, the influence of noise will be avoided to increase the yield, more over, the multiple phases clock will provide multiple receive channels to be shared concurrently.
The clock recovery system that employing the multiple phases is shown in the FIG. 1(a), the received data stream and the system""s clock will be processed by a digital signal processor 10 (DSP) to obtain the information of the relative time of the clock and the data stream, and the information will be used to determine whether the clock ahead or behind the best point of sampling, thereafter, a up/down switching signal will be sent to the multiple phases switching circuit 11 to switch the output of different phases clock., with this mechanism the proper recovered clock will be generated and the latch 12 will complete the sampling and output the received data. The FIG. 1(b) is showing the diagram of the clock of the system described above, the system will obtain 8 multiple phases clock (ck0-ck7) that spreading evenly on 360 degree, the data stream in the figure is showing the time frame of receiving data, as shown, the best clock for sampling is ck4 whose rising edge aligning preciously to the middle of two consecutive rising/falling edge of the received data, which makes the bit error rate low down to the minimum level. The operation in the FIG. 1(a) is showing a example, if the wave of the recovery clock that outputting from the multiple phases switching circuit 11 is same as the one shown in FIG. 1(c), that is, the rising edge of the starting clock is aligning to ck2, and then switching to ck3 and ck4 sequentially thru the process of the digital signal, and finally locking on the ck4, then, the clock recovery eventually being completed. However, the example in FIG. 1(c) is a better one in clock recovery, in practice, the glitch/spike that caused by the control signal of phase switching in different time frame is ought to be taken into account, as shown in the FIG. 1(d), if special attention has not been paid in the time of switching, the glitch/spike 13 will appear in clock recovery and cause error sampling. The major feature in clock recovery system is that the switching phase has to move upward or downward (positive phase or negative phase), since the starting phase can be ahead or behind the idealist phase. In prior art, in order to avoid the glitch/spike, the phase switch technology only switch one direction, for the multiple phases clock is spreading evenly on 360 degrees, one direction switching still can switch to the phase properly, however, in the application of clock recovery, one direction switching will increase the average lock-in time; for example, in a positive phase one direction switching circuit, if the proper phase is the adjacent negative phase, the phase switcher needs to switch almost 360 degrees toward the positive phase to reach the target negative phase, the data selected in the process of sampling will not be assured to be correct; the application is pretty limited.
More, the phase switching circuit is not only employed in the data recovery system, but also in a fractional-N frequency synthesizer. A conventional fractional-N frequency synthesizer accomplish the frequency synthesizing by swallow a pulse in a fixed time, as shown in FIG. 2(a) the system is comprising the phase detector 20, the charge pump 22, the voltage control oscillator 23 and the pulse swallow 24. The corresponding clock diagram is shown in FIG. 3(b), the original clock is shown in FIG. 3(a), the original clock frequency is f1=1/Ts, if a pulse is swallowed in time of Tp, which will be equivalent to the output frequency f1xe2x88x92(1/Tp) of the voltage control oscillator 22, with the control of length of the time of Tp, the non-integer multiple of f1 (reference frequency) can be synthesized, conventionally, a counter can be used to accomplish this function. But, since swallowing a pulse directly will cause a bigger clock jitter on clock signal, the multiple phase clock signal will be employed to swallow a pulse gradually in modern circuit design in order to low down the clock signal jitter caused by the sudden change of frequency. A practical example is to accomplish the all 360 degree phase switching within a certain time period, that is, to switch sequentially a complete phase within few cycles, and with which swallow a pulse gradually. The system shown in FIG. 2(b) is employing the multiple phase clock signal to swallow a pulse gradually, the difference that differing from the FIG. 2(a) is that the voltage control oscillator 23 and the pulse swallow 24 are replaced by the multiple voltage control oscillator 25 and the multiple phase switching circuit 21, within, a up/down switching signal is adapted to control the multiple phase switching circuit and further switch the output of different phase clock. The corresponding diagram of clock is shown in FIG. 3(c), the original clock is shown in FIG. 3(a), the original clock frequency is f1=1/Ts, if one fourth of a pulse is swallowed within every 3 clock cycles (3Ts) in time of Tp, a entire pulse will be swallowed within 12 clock cycles, which will be equivalent to the output frequency f1xe2x88x92(1/Tp) of the voltage control oscillator 22, with the control of the time length of Tp, the non-integer multiple of f1 (reference frequency) can be synthesized.
The operation of sequential phases switching is essential in the fractional-N frequency synthesizer described above. Therefore, to avoid the glitch/spike in phase switching is a major consideration of circuit design, in the application of clock recovery, the occurrence of glitch/spike will cause data sampling error, also the bit error rate increase; and in the application of fractional-N frequency synthesizer, the glitch/spike will response for bigger phase noise. How to avoid the glitch/spike in phase switching is a key issue when a designer designing circuit.
To this end, the primary purpose of the present invention is to develop a phase switching circuit that will switch forward/backward bi-directionally in phase switching and will avoid the glitch/spike when any time enabling the signal switching.
The primary aspect of the present invention is to provide a multiple phases switching circuit, which can be used in a multiple phase signal generator and a succeeding circuit, in the same time, the multiple phase signal generator will generate N multiple phases clock signals that spreading 360 degrees, the phase of any clock signal is ahead of the phase of the next coming clock signal, the multiple phase switching circuit comprises:
a alternative signal generator used to output n alternative signals, only one of the n signals with base xe2x80x9c1xe2x80x9d, the rest with base xe2x80x9c0xe2x80x9d, the alternative signal generator is controlled by a up/down switching signal that will change the base xe2x80x9c0xe2x80x9d signal being adjacent up/down to the base xe2x80x9c1xe2x80x9d alternative signal to base xe2x80x9c1xe2x80x9d signal, also, the alternative signal generator will be triggered by a synchronized signal to output the n alternative signals that being transformed; a multiplexer which connected electrically with the multiple phases signals generator, the alternative signal generator and the succeeding circuit, the multiplexer will receive the input of n clock signals and n alternative signals and output a target clock signal corresponding the alternative signal with base xe2x80x9c1xe2x80x9d to provide the usage for the succeeding circuit, in this case, the target clock signal is used to be a synchronized signal and feedbacks to the alternative signal generator.
Based on the above conception, the succeeding circuit that employing the multiple phases switching circuit is a data recovery system.
Based on the above conception, the succeeding circuit that employing the multiple phases switching circuit is a fractional-N frequency synthesizer.
Based on the above conception, the alternative signal generator in the multiple phases switching circuit is comprising a finite state machine that used to output n alternative signals in the same time, only one of the n signals with base xe2x80x9c1xe2x80x9d, the rest with base xe2x80x9c0xe2x80x9d, the alternative signal generator is controlled by a up/down switching signal that will change the base xe2x80x9c0xe2x80x9d signal being adjacent up/down to the base xe2x80x9c1xe2x80x9d alternative signal to base xe2x80x9c1xe2x80x9d signal; and a synchronizer that connected electrically to the output end of n alternative signals of the multiplexer and the finite state machine, also, the synchronizer will be triggered by the synchronized signal to output the n alternative signals that outputted from the finite state machine.
Based on the above conception, the synchronizer in the multiple phases switching circuit comprises n D style flip-flops.
Based on the above conception, the multiplexer in the multiple phases switching circuit comprises n phase switching units that receiving respectively the signals inputting from n clock signals and n alternative signals and generating n output signals, when the received alternative signal is with the base xe2x80x9c0xe2x80x9d and the state is disable, the output signal will be with the base xe2x80x9c0xe2x80x9d, when the received alternative signal is with the base xe2x80x9c1xe2x80x9d and the state is enable, the received clock signal will be output as the output signal; and a OR gate processor that used to receive and process n signals that outputting from n phase switching units and output the target clock signal.
Based on the above conception, the multiplexer in the multiple phases switching circuit comprises n phase switching units that receiving respectively the signals inputting from n clock signals and n alternative signals and generating n output signals, when the received alternative signal is with the base xe2x80x9c0xe2x80x9d and the state is disable, the output signal will be with the base xe2x80x9c0xe2x80x9d, when the received alternative signal is with the base xe2x80x9c1xe2x80x9d and the state is enable, the received clock signal will be output as the output signal; and a NOR gate processor that used to receive and process n signals that outputting from n phase switching units and output the target clock signal.
Based on the above conception, the multiplexer in the multiple phases switching circuit comprises n phase switching units that receiving the corresponding clock signal, the up adjacent signal and n alternative signals and then proceed a glitch/spike prevent process to generate n output signals, the glitch/spike prevent process is; when the alternative signals is with base xe2x80x9c0xe2x80x9d and the corresponding clock signal is with base xe2x80x9c0xe2x80x9d, the signal that outputting from the phase switching unit is with base xe2x80x9c0xe2x80x9d, but when the alternative signals is with base xe2x80x9c1xe2x80x9d and the prior state of the alternative signal is with base xe2x80x9c0xe2x80x9d, if the corresponding clock signal is with base xe2x80x9c1xe2x80x9d and the up adjacent clock signal is with base xe2x80x9c0xe2x80x9d, the corresponding clock signal will be outputted as the output signal that output from the phase switching unit; and a OR gate processor that used to receive and process n signals that outputting from n phase switching units and output the target clock signal.
Based on the above conception, the multiplexer in the multiple phases switching circuit comprises n phase switching units that receiving the corresponding clock signal, the up adjacent signal and n alternative signals and then proceed a glitch/spike prevent process to generate n output signals, the glitch/spike prevent process is; when the alternative signals is with base xe2x80x9c0xe2x80x9d and the corresponding clock signal is with base xe2x80x9c0xe2x80x9d, the signal that outputting from the phase switching unit is with base xe2x80x9c0xe2x80x9d, but when the alternative signals is with base xe2x80x9c1xe2x80x9d and the prior state of the alternative signal is with base xe2x80x9c0xe2x80x9d, if the corresponding clock signal is with base xe2x80x9c1xe2x80x9d and the up adjacent clock signal is with base xe2x80x9c0xe2x80x9d, the corresponding clock signal will be outputted as the output signal that output from the phase switching unit; and a NOR gate processor that used to receive and process n signals that outputting from n phase switching units and output the target clock signal.
The second aspect of the present invention is to provide a multiple phases switching circuit, which can be used in a multiple phase signal generator and a succeeding circuit, in the same time, the multiple phase signal generator will generate N multiple phases clock signals that spreading 360 degrees, the phase of any clock signal is ahead of the phase of the next coming clock signal, the multiple phase switching circuit comprises:
a alternative signal generator used to output n alternative signals, only one of the n signals with base xe2x80x9c1xe2x80x9d, the rest with base xe2x80x9c0xe2x80x9d, the alternative signal generator is controlled by a up/down switching signal that will change the signal being adjacent up/down to the base xe2x80x9c1xe2x80x9d alternative signal to base xe2x80x9c1xe2x80x9d signal; a multiplexer which connected electrically with the multiple phases signals generator, the alternative signal generator and the succeeding circuit, the multiplexer comprises n phase switching units and a OR gate processor, the phase switching units are used to receive the corresponding clock signal, the up adjacent signal and n alternative signals and then proceed a glitch/spike prevent process to generate n output signals, the glitch/spike prevent process is; when the alternative signals is with base xe2x80x9c0xe2x80x9d and the corresponding clock signal is with base xe2x80x9c0xe2x80x9d, the signal that outputting from the phase switching unit is with base xe2x80x9c0xe2x80x9d, but when the alternative signals is with base xe2x80x9c1xe2x80x9d and the prior state of the alternative signal is with base xe2x80x9c0xe2x80x9d, if the corresponding clock signal is with base xe2x80x9c1xe2x80x9d and the up adjacent clock signal is with base xe2x80x9c0xe2x80x9d, the corresponding clock signal will be outputted as the output signal that output from the phase switching unit and the OR gate processor will be used to receive and process n signals that outputting from n phase switching units and output the target clock signal for the succeeding circuit.
Based on the above conception, the succeeding circuit that employing the multiple phases switching circuit is a data recovery system.
Based on the above conception, the succeeding circuit that employing the multiple phases switching circuit is a fractional-N frequency synthesizer.
Based on the above conception, the alternative signal generator in the multiple phases switching circuit is comprising a finite state machine that used to output n alternative signals in the same time, only one of the n signals with base xe2x80x9c1xe2x80x9d, the rest with base xe2x80x9c0xe2x80x9d, the alternative signal generator is controlled by a up/down switching signal that will change the base xe2x80x9c0xe2x80x9d signal being adjacent up/down to the base xe2x80x9c1xe2x80x9d alternative signal to base xe2x80x9c1xe2x80x9d signal.
Based on the above conception, the alternative signal generator in the multiple phases switching circuit further comprises a synchronizer that connected electrically to the output end of n alternative signals of the multiplexer and the finite state machine, also, the synchronizer will be triggered by the synchronized signal to output the n alternative signals that outputted from the finite state machine.
Based on the above conception, the synchronizer in the multiple phases switching circuit comprises n D style flip-flops.
The third aspect of the present invention is to provide a multiple phases switching circuit, which can be used in a multiple phase signal generator and a succeeding circuit, in the same time, the multiple phase signal generator will generate N multiple phases clock signals that spreading 360 degrees, the phase of any clock signal is ahead of the phase of the next coming clock signal, the multiple phase switching circuit comprises: a alternative signal generator used to output n alternative signals, only one of the n signals with base xe2x80x9c1xe2x80x9d, the rest with base xe2x80x9c0xe2x80x9d, the alternative signal generator is controlled by a up/down switching signal that will change the signal being adjacent up/down to the base xe2x80x9c1xe2x80x9d alternative signal to base xe2x80x9c1xe2x80x9d signal; a multiplexer which connected electrically with the multiple phases signals generator, the alternative signal generator and the succeeding circuit, the multiplexer comprises n phase switching units and a NOR gate processor, the phase switching units are used to receive the corresponding clock signal, the up adjacent signal and n alternative signals and then proceed a glitch/spike prevent process to generate n output signals, the glitch/spike prevent process is; when the alternative signals is with base xe2x80x9c0xe2x80x9d and the corresponding clock signal is with base xe2x80x9c0xe2x80x9d, the signal that outputting from the phase switching unit is with base xe2x80x9c0xe2x80x9d, but when the alternative signals is with base xe2x80x9c1xe2x80x9d and the prior state of the alternative signal is with base xe2x80x9c0xe2x80x9d, if the corresponding clock signal is with base xe2x80x9c1xe2x80x9d and the up adjacent clock signal is with base xe2x80x9c0xe2x80x9d, the corresponding clock signal will be outputted as the output signal that output from the phase switching unit and the NOR gate processor will be used to receive and process n signals that outputting from n phase switching units and output the target clock signal for the succeeding circuit.
Based on the above conception, the succeeding circuit that employing the multiple phases switching circuit is a data recovery system.
Based on the above conception, the succeeding circuit that employing the multiple phases switching circuit is a fractional-N frequency synthesizer.
Based on the above conception, the alternative signal generator in the multiple phases switching circuit is comprising a finite state machine that used to output n alternative signals in the same time, only one of the n signals with base xe2x80x9c1xe2x80x9d, the rest with base xe2x80x9c0xe2x80x9d, the alternative signal generator is controlled by a up/down switching signal that will change the base xe2x80x9c0xe2x80x9d signal being adjacent up/down to the base xe2x80x9c1xe2x80x9d alternative signal to base xe2x80x9c1xe2x80x9d signal.
Based on the above conception, the alternative signal generator in the multiple phases switching circuit further comprises a synchronizer that connected electrically to the output end of n alternative signals of the multiplexer and the finite state machine, also, the synchronizer will be triggered by the synchronized signal to output the n alternative signals that outputted from the finite state machine, the synchronized signal the target clock signal that output from the OR gate processor.
Based on the above conception, the synchronizer in the multiple phases switching circuit comprises n D style flip-flops.
The appended drawings will provide further illustration of the present invention, together with the description, serve to explain the principles of the invention.